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Data Sheet
I 2 C Write Operation
The write operation using the I 2 C interface of the ADE7854 /
ADE7858 / ADE7868 / ADE7878 initiate when the master generates
a start condition and consists in one byte representing the
address of the ADE78xx followed by the 16-bit address of the
target register and by the value of the register.
The most significant seven bits of the address byte constitute
the address of the ADE7854 / ADE7858 / ADE7868 / ADE7878
and they are equal to 0111000b. Bit 0 of the address byte is a
ADE7854/ADE7858/ADE7868/ADE7878
read/write bit. Because this is a write operation, it has to be
cleared to 0; therefore, the first byte of the write operation is
0x70. After every byte is received, the ADE7854 / ADE7858 /
ADE7868 / ADE7878 generate an acknowledge. As registers can
have 8, 16, or 32 bits, after the last bit of the register is transmitted
and the ADE78xx acknowledges the transfer, the master gene-
rates a stop condition. The addresses and the register content
are sent with the most significant bit first. See Figure 86 for
details of the I 2 C write operation.
15
8
7
0
31
24
23
16
15
8
7
0
S 0 1 1 1 0 0 0 0
S
SLAVE ADDRESS
A MSB 8 BITS OF A LSB 8 BITS OF A
C REGISTER ADDRESS C REGISTER ADDRESS C
K K K
BYTE 3 (MSB)
OF REGISTER
A A A
C BYTE 2 OF REGISTER C BYTE 1 OF REGISTER C
K K K
BYTE 0 (LSB) OF
REGISTER
A
C
K
ACKNOWLEDGE
GENERATED BY
ADE78xx
Figure 86. I 2 C Write Operation of a 32-Bit Register
Rev. H | Page 69 of 100
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